Processes are known for fabrication of bipolar transistors having a self-aligned structure, using a first polysilicon layer for the extrinsic base contact and a second polysilicon layer for the emitter contact, for example as described in an article entitled "High speed polysilicon emitter base bipolar transistor" by Hee K. Park et al., IEEE Electron Device Letters, EDL-7 no 12 December 1986. Self-alignment of the base and the emitter allows for minimization of both the extrinsic base resistance and the collector-base junction capacitance.
Another example of a double polysilicon structure is described in an article by Warnock et al. entitled "50 GHz Self-Aligned Silicon Bipolar Transistors with Ion Implanted Base Profiles", IEEE Electron Device Letters, Vol. 11, no. 10 (Oct. 1990).
The conventional double-poly process requires first and second polysilicon layer and the resulting structure has highly non-planar topography. In particular, the topography of the polysilicon layer forming the emitter may have a sharp discontinuity in the emitter region, requiring a very thick polysilicon layer to fill the emitter gap without voids. The latter complicates subsequent processing steps, including metallization and dielectric planarization, and creates problems in contact imaging, and contact etch. The depth differential of the contact to the emitter and the contact to the sinker is very large and they are in close proximity to one another. The resulting high aspect ratio contact holes are difficult to form while preserving the underlying salicide.
There is risk from potential damage of the emitter-base junction during etching of the emitter opening in the first polysilicon layer because there is no etch stop, i.e. there is little or no etch selectivity to the underlying silicon. Damage to the emitter-base junction due to over-etching can have severe implications for the noise of the transistor for analog applications. Variable recessing of the base during silicon over etch, and consequent sidewall spacer width variability, can lead to variability in emitter width. The ensuing variations in emitter-base capacitance along the sidewall spacer edge and emitter polysilicon contact area cannot be avoided without exacerbating the topography related problems.
Furthermore, the doping in the link region of the base cannot be controlled independently of the base implant dose, leading to higher than desirable base resistance and/or emitter-base edge leakage problems.
Thus, the latter process for a double-poly self-aligned NPN bipolar transistor is complex and suffers from a number of process related problems, which lead to reliability issues in the resulting device structure.
As described in an article entitled "A high speed bipolar technology featuring self-aligned single poly base and submicrometer emitter contacts" by W. M. Huang et al. IEEE Electron Device Letters vol. 11, no. 9 September 1990, problems with etching double polysilicon structures may be avoided by fabricating the emitter contact with the first layer of polysilicon. The latter process is known as the "STRIPE" (self-aligned trench isolated polysilicon electrodes) process. The polysilicon layer is etched to define trenches for isolating the emitter region from the base regions. A low energy boron implant into the trench region defines a link region. Then the trench is filled with oxide and then the emitter region is n+ doped by an arsenic implant. This process reduces the possibility of etch damage of the active emitter area and avoids the highly non-planar topography of the conventional double poly process. However, other process related problems remain in the PE and subsequent processing steps, including etching of the polysilicon layer to form narrow trenches (0.2 to 0.4 .mu.m) for isolation between the emitter and base regions.
Another approach to forming a single polysilicon self-aligned bipolar transistor, known as the ASPECT process, comprises forming a p type base region in the device well similarly as described above, and then forming an emitter structure by depositing a layer of polysilicon overall, patterning and etching the polysilicon to leave an emitter structure in the form of a mesa, and isolating the emitter mesa with oxide sidewall spacers, before forming contacts to the base contact region surrounding the emitter mesa. However, the latter process does not avoid the risk of damage to the underlying silicon layer in the base contact region during overetching of the polysilicon layer region.
Further examples of single polysilicon bipolar transistors are discussed in section 7.9.2 of Wolf "Silicon Processing for the VLSI Era", vol. 2-Process Integration; (1990), pages 516 to 520; an article by Chen et al, entitled "Advanced bipolar transistor with self-aligned ion-implanted base and w/poly emitter", IEEE Transactions on Electron Devices Vol. 35, no. 8, (Aug. 1988); and IEEE 1988 Bipolar Circuits and Technology meeting, paper no. 9.5, "Electron Recombination at the Silicided Base Contact of an Advanced Self-aligned Polysilicon Emitter" by de Jong et al.